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Computer Architecture is the bridge between the software you write and the physical hardware that runs it. When you write a line of Python, it is compiled down through several layers until it becomes a stream of simple machine instructions that the CPU executes one at a time. In Computer Fundamentals you learned that the CPU fetches, decodes, and executes instructions. Now we look closer: what those instructions look like (assembly and the instruction set), why the CPU keeps several layers of cache, and how modern processors execute many instructions at once through pipelining and branch prediction. This lesson connects high-level code to machine execution, so that performance ideas like "cache-friendly" code stop being mysterious.
The compiler translates a high-level language into assembly (human-readable machine code), and the assembler turns that into binary instructions the CPU can execute.
The ISA is the contract between software and hardware: the set of instructions a CPU understands, the registers it exposes, and how memory is addressed. Programs written for one ISA do not run on another without recompilation.
Assembly is the lowest human-readable level. Instructions move values between registers and memory, perform arithmetic, and branch.
Cache is a small, fast memory between the CPU and RAM. Programs access data with locality — the same data or nearby data is used again soon — so the cache stores recently used values.
| Level | Size | Speed | Shared? |
|---|---|---|---|
| L1 | Tens of KB per core | Fastest | No (per core) |
| L2 | Hundreds of KB per core | Very fast | No (per core) |
| L3 | Several MB | Fast | Yes (shared) |
| RAM | Gigabytes | Slower | Yes |
When the CPU finds data in cache it is a hit (fast). When it must go to RAM it is a miss (slow). Fewer misses mean faster programs.
Pipelining overlaps the execution of multiple instructions: while one instruction is executing, the next is being decoded and the one after that is being fetched.
This increases throughput: more instructions finish per second, even though each still takes three stages.
A superscalar CPU can issue more than one instruction per clock cycle by having multiple execution units. Branch prediction guesses the direction of a branch before it is known, so the pipeline can keep filling instead of stalling. A wrong guess must be discarded, but a right guess saves a lot of time.
Virtual memory gives each program its own view of a large, private address space, while the hardware (with the operating system) maps those virtual addresses to real physical memory. The CPU uses a Memory Management Unit (MMU) and a small cache of translations called the TLB to make this fast.
| Architecture | Organization | |
|---|---|---|
| What it is | The instruction set and programmer-visible behavior | How the hardware implements it |
| Example | x86 ISA | Pipelines, caches, ALUs |
| Changes | Rarely (must stay compatible) | Often (each new chip) |